1) Field of the Invention
This invention relates generally to fabrication of semiconductor devices particularly to the fabrication of implanted doped regions in a semiconductor device that has a graded junction
2) Description of the Related Art
With higher levels of integrated circuits on semiconductor chips and the need for faster transistors in these circuits, the FET transistor must maximize all aspects of semiconductor physics to fabricate transistors in these circuits with faster switching speed.
As the transistor scaling to smaller dimension, the inventor have found that high Vt NMOS transistor is facing a problem with voltage limitation. Thermal cycle was limited because of the consideration of logic device in the wafer. An aspect of this invention address issue.
In crystalline solids, such as monocrystalline silicon, the atoms which make up the solid are spatially arranged in a periodic fashion. This periodic arrangement of atoms in a crystal is called a lattice. The crystal lattice always contains a volume which is representative of the entire lattice and it is regularly repeated throughout the crystal. The directions in a lattice are expressed as a set of three integers with the same relationship as the components of a vector in that direction. The three vector components are given in multiples of the basic vectors. For example, in cubic lattices, such as silicon which has a diamond crystal lattice, the body diagonal has the components of 1a, 1b, and 1c and this diagonal exist along the [111] direction with the [ ] brackets being used to denote a specific direction. However, many directions in a crystal are equivalent, depending on the arbitrary choice of orientation of the axes. Such equivalent directions are denoted with < > brackets and, for example, crystal directions in the cubic lattice [100], [010], and [001] are all crystallographically equivalent and are <100> directions. Since these directions will also be on the negative side of the origin, as arbitrarily defined, they also are identified with a (−) over the specific negative integer, such as [ 100], [0 10], and [00 1] for <100> directions. Unless specifically stated or shown in the following description in this application, a crystal direction includes both positive and negative integers.
Planes in a crystal also can be determined with a set of three integers h, k, and l. They are used to define a set of parallel planes and each set of three integers in ( ) parentheses identify a specific plane. As in the case of directions, many planes in a lattice are equivalent and the indices of such equivalent planes are denoted by { } parentheses. For cubic lattices, direction [k,l,m] is perpendicular to a plane with the identical three integers (k,l,m). Thus, if either a direction or a plane of a cubic lattice is known, its perpendicular counterpart can be quickly determined without calculation. For example, for planes of equivalent symmetry such as {100} plane, the equivalent planes are (100), (010), (001), (100), (010), and (001). Like the crystal direction, the crystal plane in the following description in this application includes both positive and negative integers unless specifically stated otherwise.
General terminology is: ( ) for a certain plane; { } for a group of planes; [ ] for a certain direction; < > for a group of directions.
Ion implant processes are important to forming doped regions in substrates. The depth to which an ion becomes implanted is proportional to its kinetic energy. The implanted distribution in an amorphous target is roughly a Gaussian distribution characterized by a mean, known as the range, and a standard deviation, known as the straggle. In a single crystal target, the range and straggle for a given implant may be different than that in amorphous material, due to a phenomena known as channeling. Higher ion energy, higher silicon temperature, and the growth of silicon dioxide layers on the silicon all tend to dechannel implants. In any event, range and straggle data for various materials including silicon, silicon dioxide, and photoresist have been determined.
The more relevant technical art in the patent literature is as follows: U.S. Pat. No. 5,970,300 (Buynoski) shows an alignment of a FET on a wafer.
U.S. Pat. No. 6,566,204 (Wang, et al.) teaches the use of mask shadowing and angled implantation in fabricating asymmetrical field-effect transistors.
U.S. Pat. No. 6,599,804 (Bulucea, et al.)shows a fabrication of field-effect transistor for alleviating short-channel effects.
U.S. Pat. No. 4,728,617 (Woo, et al.) shows a method of fabricating a MOSFET with graded source and drain regions using a high tilt I/I.
However, there is a need for an improved process and device.